1. Technical Field
The present invention generally relates to a semiconductor device and a method of fabricating the semiconductor device, and more particularly, to a semiconductor device having non-volatile memories and a method of fabricating the semiconductor device.
2. Description of the Related Art
In recent years, non-volatile memories that are data rewritable semiconductor devices are widely used. In the field of non-volatile memory, studies and developments of smaller memory cells are being made to achieve larger memory capacities. Non-volatile memories include flash memories having such structures as a MONOS (Metal Oxide Nitride Oxide Silicon) structure and a SONOS (Silicon Oxide Nitride Oxide Silicon) structure having charges accumulated in an ONO (Oxide/Nitride/Oxide) film. Among those flash memories, there is a flash memory having bit lines that are embedded in the semiconductor substrate and serve as a source region and a drain region for purpose of miniaturization of memory cells (see U.S. Pat. No. 6,011,725).
Referring to prior art FIGS. 1A (prior art) through 3C (prior art), a conventional flash memory is described. In FIGS. 1A (prior art), 2A (prior art), and 3A (prior art), the ONO film 14, the interlayer insulating film 30, the wiring layers 34, and the protection film 36 are not shown. As shown in prior art FIGS. 1A (prior art) through 1C (prior art), ion implantation is performed to form n-type bit lines 12 in a p-type silicon semiconductor substrate 10. The bit lines 12 extend in the direction of B-B shown in FIG. 1A (prior art). An ONO film 14 is formed on the semiconductor substrate 10, and word lines 16 are formed on the ONO film 14. The formation of the word lines 16 is carried out by forming a polycrystalline silicon film on the entire surface, followed by conventional exposure or etching. A bit-line contact region 40 that will be described later is provided for every several word lines 16.
Referring now to prior art FIGS. 2A (prior art) through 2C (prior art), sidewall layers 20 formed from silicon nitride film are formed on both sides of each of the word lines 16. The portions between the word lines 16 are filled with the sidewall layers 20. As shown in prior art FIGS. 2A (prior art) and 2C (prior art), the bit-line contact region 40 is not filled with the sidewall layers 20, but sidewall layers 20a are formed at side portions of the word lines 16a on both sides of the bit-line contact region 40.
Referring now to prior art FIGS. 3A (prior art) through 3C (prior art), an interlayer insulating film 30 is formed over the word lines 16, the sidewall layers 20, and the ONO film 14. Contact holes 32 connecting to the bit lines 12 in the bit-line contact region 40 are formed in the interlayer insulating film 30 and the ONO film 14. The contact holes 32 are filled with plug metal. Wiring layers 34 that extend in the longitudinal direction of the bit lines 12 and connect to the bit lines 12 via the contact holes 32 are formed on the interlayer insulating film 30. A protection film 36 is formed over the wiring layers 34 and the interlayer insulating film 30. Thus, the conventional memory is completed.
In this flash memory, the bit lines 12 are formed from a diffusion layer through ion implantation. Therefore, the bit lines 12 have higher resistance than the metal material of the wiring layers 34 or the like. As a result, only with the bit lines 12, the writing and erasing performances in the memory cells deteriorate. To counter this problem, at intervals of several word lines 16, the wiring layers 34 made of a metal having lower resistance than the bit lines 12 are connected to the bit lines 12 via the contact holes 32. With this arrangement, degradation of the writing and erasing performances is restrained. To reduce the area of the memory cell region, the bit-line contact region 40 extending in the longitudinal direction of the word lines 16 is provided for every several word lines 16, and the contact holes 32 are formed in the bit-line contact region 40.
There are the following problems with the conventional art. First, as shown in FIG. 3A (prior art), when the word lines 16 are formed, the width WL2 of each of the word lines 16a on both sides of the bit-line contact region 40 is larger than the width WL1 of each of the word lines 16 neighboring one another. For example, in a case where WL1 is 150 nm, WL 2 is 170 nm. This is due to a proximity effect caused by the exposure of the resist pattern of the word lines 16. In this structure, the variation in the widths of the word lines 16 is large. Since the word lines 16 also serve as the control gate, the variation in the electric characteristics of the memory cells becomes larger as the variation in the widths of the word lines 16 becomes larger due to the proximity effect.
While each of the sidewall layers 20 has its sides both in contact with the word lines 16, each of the sidewall layers 20a facing the bit-line contact region 40 only has one side in contact with each corresponding word line 16a. Because of this, each of the sidewall layers 20 between the word lines 16 has a different cross section from the cross section of each of the sidewall layers 20a facing the bit-line contact region 40. Also, the width SW1 of each of the sidewall layers 20 between the word lines 16 is different from the width SW2 of each of the sidewall layers 20a facing the bit-line contact region 40. For example, in a case where SW1 is 80 nm, SW2 is 90 nm. In this structure, variations in the widths and shapes of the sidewall layers 20 are large. The sidewall layers 20 are made of insulating film such as silicon nitride film having high stress. With this arrangement, the stress applied from the sidewall layers 20 to the memory cells on both sides of the bit-line contact region 40 differs from the stress applied to the other memory cells. As a result, the variation in the electric characteristics of the memory cells becomes large.
If there is misalignment of exposure in forming the contact holes 32 with respect to the bit lines 12, the contact holes 32 are formed directly on the semiconductor substrate 10. If this happens, junction current flows between the semiconductor substrate 10 and the plug metal in the contact holes 32. As a result, current leakage is caused between the semiconductor substrate and the bit lines 12.